In the art of semiconductor circuit manufacture, it is desirable to provide very fast components in the smallest total area. When fabricating such circuitry, limitations to the optimal size are encountered not only as a result of the physical constraints imposed by equipment and processing capabilities but also as a result of the inherent physical properties of the materials and their properties under the conditions encountered during processing. Ideal combinations of materials have been theorized, given their physical and electrical properties; but the actual fabrication of components utilizing those combinations frequently cannot be realized. Factors which contribute to constraints on fabrication include adhesion of desired electrode and dielectric materials to the substrate materials and to other adjacent layer materials, temperature stability given the processing requirements of the related materials, chemical processing stability, deposition and etching processing requirements for the individual material and, of course, electrical compatibility of the materials.
Specifically in the fabrication of capacitor structures, one successively deposits films of a conductive material comprising a first electrode, a dielectric material sandwich layer, and a second layer of conductive material comprising the second electrode. Necessarily, as discussed above, achieving the desired dimensions in both film thickness and capacitor width is challenging. Processing techniques for both the deposition and removal of films are well known, however, depositing the desired combination of conductor-dielectric-conductor films within the desired tolerances is not always possible.
A known combination of materials for semiconductor capacitor structures is detailed in U.S. Pat. No. 5,046,043 of Miller et al wherein a thin film ferroelectric layer, such as PbTiO, is sandwiched between two electrode layers, of platinum for example. Additional Miller et al patents, specifically U.S. Pat. Nos. 4,946,710 and 5,046,043 set forth methods for preparing and fabricating thin films of ferroelectric dielectric layers for use in semiconductor capacitor structures. Although the Miller teachings do provide improved sol gel methods for depositing thin films, the thin film deposition process is merely one aspect of the total fabrication process for creating the desired capacitor structure. One cannot obtain the ideal tolerances for a platinum-ferroelectric-platinum capacitor structures merely by following the Miller teachings, alone or in combination with other available teachings for capacitor manufacture.
It is, therefore, one of the objectives of the present invention to provide a superior capacitor structure.
It is a further objective of the invention to provide a method for fabricating a superior capacitor structure.
It is yet another objective of the invention to provide a high capacity structure in a small area on a semiconductor substrate.